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  tm jan 2013 fdd8424h_f085a dual n & p-channel powertrench ? mosfet ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com 1 fdd8424h _f085a dual n & p-channel powertrench ? mosfet n-channel: 40v, 20a, 24m ? p-channel: -40v, -20a, 54m ? features q1: n-channel ? max r ds(on) = 24m ? at v gs = 10v, i d = 9.0a ? max r ds(on) = 30m ? at v gs = 4.5v, i d = 7.0a q2: p-channel ? max r ds(on) = 54m ? at v gs = -10v, i d = -6.5a ? max r ds(on) = 70m ? at v gs = -4.5v, i d = -5.6a ? fast switching speed ? rohs compliant general description these dual n and p-channel enhancement mode power mosfets are produced using fairchild semiconductor?s advanced powertrench proces s that has been especially tailored to minimize on-state resistance and yet maintain superior switching performance. application ? inverter ? h-bridge mosfet maximum ratings t c = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 40 -40 v v gs gate to source voltage 20 20 v i d drain current - continuous (package limited) 20 -20 a - continuous (silicon limited) t c = 25c 26 -20 - continuous t a = 25c 9.0 -6.5 - pulsed 55 -40 p d power dissipation for single operation t c = 25c (note 1) 30 35 w t a = 25c (note 1a) 3.1 t a = 25c (note 1b) 1.3 e as single pulse avalanche energy (note 3) 29 33 mj t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case, single operation for q1 (note 1) 4.1 c/w r jc thermal resistance, junction to case, single operation for q2 (note 1) 3.5 device marking device package reel size tape width quantity fdd8424h fdd8424h_f085a to-252-4l 13? 12mm 2500 units dual dpak 4l d1/d2 g2 s2 g1 s1 n-channel p-channel d1 d2 s1 g1 s2 g2 ? qualified to aec q101
2 electrical characteristics t j = 25c unless otherwise noted symbol parameter test conditions type min typ max units off characteristics bv dss drain to source breakdown voltage i d = 250 a, v gs = 0v i d = -250 a, v gs = 0v q1 q2 40 -40 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c i d = -250 a, referenced to 25 c q1 q2 34 -32 mv/ c i dss zero gate voltage drain current v ds = 32v, v gs = 0v v ds = -32v, v gs = 0v q1 q2 1 -1 a i gss gate to source leakage current v gs = 20v, v ds = 0v q1 q2 100 100 na na on characteristics v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = -250 a q1 q2 1 -1 1.7 -1.6 3 -3 v ? v gs(th) ? t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c i d = -250 a, referenced to 25 c q1 q2 -5.3 4.8 mv/ c r ds(on) static drain to source on resistance v gs = 10v, i d = 9.0a v gs = 4.5v, i d = 7.0a v gs = 10v, i d = 9.0a, t j = 125 c q1 19 23 29 24 30 37 m ? v gs = -10v, i d = -6.5a v gs = -4.5v, i d = -5.6a v gs = -10v, i d = -6.5a, t j = 125 c q2 42 58 62 54 70 80 g fs forward transconductance v ds = 5v, i d = 9.0a v ds = -5v, i d = -6.5a q1 q2 29 13 s dynamic characteristics c iss input capacitance q1 v ds = 20v, v gs = 0v, f = 1mhz q2 v ds = -20v, v gs = 0v, f = 1mhz q1 q2 750 1000 1000 1330 pf c oss output capacitance q1 q2 115 140 155 185 pf c rss reverse transfer capacitance q1 q2 75 75 115 115 pf r g gate resistance f = 1mhz q1 q2 1.1 3.3 ? switching characteristics t d(on) turn-on delay time q1 v dd = 20v, i d = 9.0a, v gs = 10v, r gen = 6 ? q2 v dd = -20v, i d = -6.5a, v gs = -10v, r gen = 6 ? q1 q2 7 7 14 14 ns t r rise time q1 q2 13 3 24 10 ns t d(off) turn-off delay time q1 q2 17 20 31 36 ns t f fall time q1 q2 6 3 12 10 ns q g(tot) total gate charge q1 v gs = 10v, v dd = 20v, i d = 9.0a q2 v gs = -10v, v dd = -20v, i d = -6.5a q1 q2 14 17 20 24 nc q gs gate to source charge q1 q2 2.3 3.0 nc q gd gate to drain ?miller? charge q1 q2 3.2 3.6 nc ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
3 notes: 1. r ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. starting t j = 25c, n-ch: l = 0.3mh, i as = 14a, v dd = 40v, v gs = 10v; p-ch: l = 0.3mh, i as = -15a, v dd = -40v, v gs = -10v. a. 40c/w when mounted on a 1 in 2 pad of 2 oz copper b. 96c/w when mounted on a minimum pad of 2 oz copper b. 96c/w when mounted on a minimum pad of 2 oz copper q1 q2 a. 40c/w when mounted on a 1 in 2 pad of 2 oz copper scale 1 : 1 on letter size paper scale 1 : 1 on letter size paper electrical characteristics t j = 25c unless otherwise noted drain-source diod e characteristics symbol parameter test conditions type min typ max units v sd source to drain diode forward voltage v gs = 0v, i s = 9.0a (note 2) v gs = 0v, i s = -6.5a (note 2) q1 q2 0.87 0.88 1.2 -1.2 v t rr reverse recovery time q1 i f = 9.0a, di/dt = 100a/s q2 i f = -6.5a, di/dt = 100a/s q1 q2 25 29 38 44 ns q rr reverse recovery charge q1 q2 19 29 29 44 nc ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
4 typical characteristics (q1 n-channel) t j = 25c unless otherwise noted figure 1. 01234 0 10 20 30 40 50 60 v gs = 4.5v v gs = 4.0v v gs = 3.5v pulse duration = 80 s duty cycle = 0.5%max v gs = 3.0v v gs = 10v i d , drain current (a) v ds , drain to source voltage (v) on- region characteristics figure 2. 0 102030405060 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 4.5v v gs = 4.0v pulse duration = 80 s duty cycle = 0.5%max normalized drain to source on-resistance i d , drain current(a) v gs = 3.5v v gs = 3.0v v gs = 10v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i d = 9a v gs = 10v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 10 20 30 40 50 pulse duration = 80 s duty cycle = 0.5%max t j = 125 o c t j = 25 o c i d = 9a r ds(on) , drain to source on-resistance ( m ? ) v gs , gate to source voltage (v) o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 10 20 30 40 50 60 v ds = 5v pulse duration = 80 s duty cycle = 0.5%max t j = -55 o c t j = 25 o c t j = 150 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.3 0.6 0.9 1.2 1.5 0.001 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0v i s , reverse drain current (a) v sd , body diode forward voltage (v) 60 s o u r c e t o d r a i n d i o d e forward voltage vs source current ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
5 figure 7. 0 4 8 12 16 0 2 4 6 8 10 i d = 9a v dd = 25v v dd = 20v v dd = 15v q g , gate charge(nc) v gs , gate to source voltage(v) gate charge characteristics figure 8. 0.1 1 10 100 1000 2000 30 f = 1mhz v gs = 0v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 40 c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 100 1 10 t j = 125 o c t j = 25 o c t av , time in avalanche(ms) i as , avalanche current(a) 30 u n c l a m p e d i n d u c t i v e switching capability f i g u r e 1 0 . m a x i m u m c o n t i n u o u s d r a i n current vs case temperature 25 50 75 100 125 150 0 5 10 15 20 25 30 limited by package r jc = 4.1 o c/w v gs = 4.5v v gs = 10v i d , drain current (a) t c , case temperature ( o c ) f i g u r e 1 1 . f o r w a r d b i a s s a f e operating area 11 0 0.1 1 10 100 10us dc 10ms 1ms 100us single pulse t j = max rated r jc = 4.1 o c/w t c = 25 o c this area is limited by r ds(on) v ds , drain to source voltage (v) i d , drain current (a) 80 figure 12. 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 100 1000 10000 v gs = 10v single pulse r jc = 4.1 o c/w p ( pk ) , peak transient power (w) t, pulse width (s) i = i 25 for temperatures above 25 o c derate peak current as follows: 150 t c ? 125 ----------------------- - t c = 25 o c s i n g l e p u l s e m a x i m u m power dissipation typical characteristics (q1 n-channel) t j = 25c unless otherwise noted ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
6 figure 13. transient thermal response curve 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 0.1 1 0.005 duty cycle-descending order normalized thermal impedance, z jc t, rectangular pulse duration (s) d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse r jc = 4.1 o c/w 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c typical characteristics (q1 n-channel) t j = 25c unless otherwise noted ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
8 typical characteristics (q2 p-channel) 01234 0 10 20 30 40 v gs = - 3v v gs = - 4v v gs = - 10v v gs = - 3.5v v gs = - 4.5v pulse duration = 80 s duty cycle = 0.5%max -i d , drain current (a) -v ds , drain to source voltage (v) figure 14. on- region characteristics 0 10203040 0.5 1.0 1.5 2.0 2.5 3.0 v gs = -10v v gs = -4.5v v gs = -3v v gs = -4v v gs = -3.5v pulse duration = 80 s duty cycle = 0.5%max normalized drain to source on-resistance - i d , drain current(a) figure 15. normalized on-resistance vs drain current and gate voltage figure 16. normalized on-resistance vs junction temperature -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = -6.5a v gs = -10v normalized drain to source on-resistance t j , junction temperature ( o c ) 24681 0 0 40 80 120 160 pulse duration = 80 s duty cycle = 0.5%max t j = 125 o c t j = 25 o c i d = -6.5a r ds(on) , drain to source on-resistance ( m ? ) -v gs , gate to source voltage (v) figure 17. on-resistance vs gate to source voltage figure 18. transfer characteristics 12345 0 10 20 30 40 v ds = -5v pulse duration = 80 s duty cycle = 0.5%max t j = -55 o c t j = 25 o c t j = 150 o c - i d , drain current (a) -v gs , gate to source voltage (v) figure 19. source to drain diode forward voltage vs source current 0.0 0.3 0.6 0.9 1.2 1.5 0.001 0.01 0.1 1 10 40 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) t j = 25c unless otherwise noted ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
typical characteristics (q2 p-channel) t j = 25c unless otherwise noted figure 20. gate ch arge characteristics 048121620 0 2 4 6 8 10 v dd = -25v v dd = -20v -v gs , gate to source voltage(v) q g , gate charge(nc) v dd = -15v i d = -6.5a 0.1 1 10 100 1000 30 f = 1mhz v gs = 0v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss 40 2000 figure 21. capacitance vs drain to source voltage figure 22. unclamped inductive switching capability 0.001 0.01 0.1 1 10 100 1 10 t j = 25 o c t j = 125 o c t av , time in avalanche(ms) - i as , avalanche current(a) 30 f i g u r e 2 3 . m a x i m u m c o n t i n u o u s d r a i n current vs case temperature 25 50 75 100 125 150 0 5 10 15 20 25 r jc = 3.5 o c/w v gs = - 4.5v v gs = - 10v -i d , drain current (a) t c , case temperature ( o c ) figure 24 11 0 0.1 1 10 100 dc 10ms 1ms 100us 10us this area is limited by r ds(on) 100 single pulse t j = max rated r jc = 3.5 o c/w t c = 25 o c -i d , drain current (a) -v ds , drain to source voltage (v) 80 . f o r w a r d b i a s s a f e operating area figure 25. 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 100 1000 10000 v gs = -10v single pulse r jc = 3.5 o c/w p ( pk ) , peak transient power (w) t, pulse width (s) i = i 25 for temperatures above 25 o c derate peak current as follows: 150 t c ? 125 ----------------------- - t c = 25 o c single pulse maximum power dissipation 9 ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
typical characteristics (q2 p-channel) t j = 25c unless otherwise noted figure 26. transient thermal response curve 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 0.1 1 2 duty cycle-descending order normalized thermal impedance, z jc t, rectangular pulse duration (s) d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse r jc = 3.5 o c/w 0.005 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c 10 ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
11 ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com fdd8424h_f085a dual n & p-channel powertrench ? mosfet
trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditio ns, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? accupower? ax-cap?* bitsic ? build it now? coreplus? corepower? crossvolt ? ctl? current transfer logic? deuxpeed ? dual cool? ecospark ? efficentmax? esbc? fairchild ? fairchild semiconductor ? fact quiet series? fact ? fast ? fastvcore? fetbench? flashwriter ? * fps? f-pfs? frfet ? global power resource sm green bridge? green fps? green fps? e-series? g max ? gto? intellimax? isoplanar? marking small speakers sound louder and better? megabuck? microcoupler? microfet? micropak? micropak2? millerdrive? motionmax? motion-spm? mwsaver? optohit? optologic ? optoplanar ? powertrench ? powerxs? programmable active droop? qfet ? qs? quiet series? rapidconfigure? saving our world, 1mw/w/kw at a time? signalwise? smartmax? smart start? solutions for your success? spm ? stealth? superfet ? supersot?-3 supersot?-6 supersot?-8 supremos ? syncfet? sync-lock? ?* the power franchise ? ? tinyboost? tinybuck? tinycalc? tinylogic ? tinyopto? tinypower? tinypwm? tinywire? transic ? trifault detect? truecurrent ? * serdes? uhc ? ultra frfet? unifet? vcx? visualmax? voltageplus? xs? ? ? tm datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the ri ght to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fair child semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts ex perience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing de lays. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages cu stomers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our custom ers to do their part in stopping this practice by buying direct or from authorized distributors. rev. i61 tm ? 12 ?2013 fairchild semiconductor corporation fdd8424h_f085a rev.c1 www.fairchildsemi.com


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